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| ds07-13748-1e fujitsu semiconductor data sheet copyright?2006 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prev ent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90860e series mb90867e(s), mb90f867e(s), mb90v340e-101/102 description mb90860e-series with flash rom is especially desig ned for automotive and other industrial applications. with the new 0.35 m cmos technology, fujitsu now offers on-chi p flash rom program memory up to 512 kbytes. the power supply (3 v) is supplied to the internal mcu co re from an internal regulator circuit. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an in ternal 42 ns instruction cycle time from an external 4 mhz clock. the unit features an 8 channel output compare unit and 8 channel input capture unit with 2 separate 16-bit free running timers. 4 uarts constitute additiona l functionality for communication purposes. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller.
mb90860e series 2 features ? cpu instruction system best suited to controller wide choice of data types (bit, byte, word, and long word) wide choice of addressing modes(23 types) enhanced multiply-divide instru ctions and reti instructions enhanced high-precision computing with 32-bit accumulator instruction system compatible with hi gh-level language (c language) and multitask employing system stack pointer enhanced various pointer indirect instructions barrel shift instructions increased processing speed 4-byte instruction queue ? serial interface uart (lin/sci) : up to 4 channels equipped with full-duplex double buffer clock-asynchronous or clock-synchronous serial transmission is available i 2 c interface* : up to 2 channels up to 400 kbits/s transfer rate ? interrupt controller powerful interrupt function powerful 8-level, 34-condition interrupt feature up to 16 external interrupts are supported automatic data transfer function independent of cpu expanded intelligent i/o service function (ei 2 os) : up to 16 channels ? i/o port general-purpose input/output port (cmos output) - 80 ports (devices without s-suffix) - 82 ports (devices with s-suffix) ? 8/10-bit a/d converter 8/10-bit a/d converter : 24 channels resolution is selectable between 8-bit and 10-bit. activation by external trigger input is allowed. conversion time : 3 s (at 24-mhz machine clock, including sampling time) program patch function ? timer time-base timer, clock timer, watchdog timer : 1 channel 8/16-bit ppg timer : 8-bit 16 channels, or 16-bit 8 channels 16-bit reload timer : 4 channels 16-bit input/output timer - 16-bit free run timer : 2 channel (frt0 : icu 0/1/2/3, ocu 0/1/2/3, frt1 : icu 4/5/6/7, ocu 4/5/6/7) - 16-bit input captur e: (icu) : 8 channels - 16-bit output compare : (ocu) : 8 channels mb90860e series 3 ? variety of mode low power consumption (standby) mode sleep mode (a mode that halts cpu operating clock) main timer mode (time-base timer mode that is transferred from main clock mode) pll timer mode (time-base timer mode that is transferred from pll clock mode) watch mode (a mode that operates sub clock and clock timer only) stop mode (a mode that stops oscillation clock and sub clock) cpu blocking operation mode ? technology 0.35 m cmos technology * : i 2 c license : purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these com- ponents in an i 2 c system provided that the system conforms to the i 2 c standard specificat ion as defined by philips. mb90860e series 4 product lineup (continued) mb90867e(s) mb90f867e(s) mb90v340e-101/102 cpu f 2 mc-16lx cpu type mask rom product flash me mory product evaluation product system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (4 mhz osc. pll 6) rom mask rom 128 kbytes flash memory 128 kbytes external ram 6 kbytes 6 kbytes 30 kbytes emulator-specific power supply* 1 ? yes technology 0.35 m cmos with on-chip voltage regulator for internal power supply 0.35 m cmos with on-chip voltage regulator for internal power supply + flash memory with on-chip charge pump for programming voltage 0.35 m cmos with on-chip voltage regulator for internal power supply operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/d converter/flash programming 4.5 v to 5.5 v : at using external bus 5 v 10 % temperature range ? 40 c to + 105 c ? package qfp-100, lqfp-100 pga-299 uart 4 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 2 channels 8/10-bit a/d converter 24 channels 10-bit or 8-bit resolution conversion time : min 3 s include sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = machine clock frequency) supports external event count function 16-bit i/o timer (2 channels) signals an interrupt when overflowing supports timer clear when a match wi th output compare (ch.0, ch.4) operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys = machine clock freq.) i/o timer 0 (clock input frck0) corre sponds to icu 0/1/2/3, ocu 0/1/2/3 i/o timer 1 (clock input frck1) corre sponds to icu 4/5/6/7, ocu 4/5/6/7 16-bit output compare (8 channels) signals an interrupt when 16-bit i/o timer match output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture (8 channels) rising edge, falling edge or rising & falling edge sensitive signals an interrupt upon external event part number parameter mb90860e series 5 (continued) *1 : it is setting of jumper switch (t ool vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. *2 : embedded algorithm is a trade mark of advanced micro devices inc. mb90867e(s) mb90f867e(s) mb90v340e-101/102 8/16-bit programmable pulse generator (8 channels) supports 8-bit and 16-bit operation modes sixteen 8-bit reload counters sixteen 8-bit reload registers for l pulse width sixteen 8-bit reload registers for h pulse width a pair of 8-bit reload counters can be conf igured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = machine clock frequency, fosc = oscillation clock frequency) can interface ? 3 channels external interrupt (16 channels) can be used rising edge, falling edge, starting up by h/l level input, external interrupt, expanded intelligent i/o services (ei 2 os) and dma d/a converter ? 2 channels up to 100 khz sub clock for low power operation devices without ?s?-suffix only for mb90v340e- 102 i/o ports virtually all external pins can be used as general purpose i/o port all push-pull outputs bit-wise settable as input/output or peripheral signal settable in pin-wise of 8 as cmos schmitt trigger/automotive inputs (default) ttl input level settable for external bus (32-pin only for external bus) flash memory supports automatic programming, embedded algorithm tm * 2 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 20 years boot block configuration erase can be performed on each block block protection with external programming voltage flash security feature for prot ecting the content of the flash ? part number parameter mb90860e series 6 pin assignments mb90v340e-101/102 (continued) (top view) (fpt-100p-m06) * : x0a, x1a : mb90v340e-102 p40, p41 : mb90v340e-101 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 p04/ad04/int12 p2 3 /a19/ppgf(e) p22/a1 8 /ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9( 8 ) p17/ad15/ s ck4 p16/ad14/ s ot4 p15/ad1 3 / s in4 x1 v ss vcc p14/ad12/ s ck 3 p1 3 /ad11/ s ot 3 p12/ad10/ s in 3 /int11r p11/ad09/tot1 p10/ad0 8 /tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int1 3 x0 3 0 1 8 p75/an21/int5 p0 3 /ad0 3 /int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int 8 pa1/tx0 pa0/rx0/int 8 r p97/out 3 p96/out2 p95/out1 p94/out0 p9 3 /ppg7(6) p92/ppg5(4) p91/ppg 3 (2) p90/ppg1(0) v ss vcc p 8 7/ s ck1 p 8 6/ s ot1 p 8 5/ s in1 p 8 4/ s ck0/int15r p 83 / s ot0/tot2 p 8 2/ s in0/tin2/int14r p 8 1/tot0/ckot/int1 3 r p 8 0/tin0/adtg/int12r p77/an2 3 /int7 p76/an22/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a2 3 /in 3 p 3 0/ale/in4 p 3 4/hrq/out4 p56/an14/da00 p55/an1 3 p54/an12/tot 3 p5 3 /an11/tin 3 p52/an10/ s ck2 p51/an9/ s ot2 p50/an 8 / s in2 p47/ s cl1 p46/ s da1 p45/ s cl0/frck1 p44/ s da0/frck0 p4 3 /in7/tx1 p42/in6/rx1/int9r c v ss vcc p41/x1a * p40/x0a * p 3 7/clk/out7 p 3 6/rdy/out6 qfp - 100 21 20 17 16 19 1 8 15 14 1 3 12 11 26 25 24 2 3 22 27 2 8 29 4 3 56 29 710 8 0 51 5 8 71 70 67 66 69 6 8 65 64 6 3 62 61 76 75 74 7 3 72 77 7 8 79 54 5 3 55 56 52 59 57 60 p57/an15/da01 p74/an20/int4 p7 3 /an19/int 3 p72/an1 8 /int2 p60/an0/ppg0(1) p61/an1/ppg2( 3 ) p62/an2/ppg4(5) p6 3 /an 3 /ppg6(7) p64/an4/ppg 8 (9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) v ss p70/an16/int0 p71/an17/int1 avcc avrh avrl av ss r s t p 3 1/rd/in5 p 3 2/wrl/wr/rx2/int10r p 33 /wrh/tx2 p 3 5/hak/out5 mb90860e series 7 (continued) (top view) (fpt-100p-m05) * : x0a, x1a : mb90v340e-102 p40, p41 : mb90v340e-101 75 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 p04/ad04/int12 p2 3 /a19/ppgf(e) p22/a1 8 /ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9( 8 ) p17/ad15/ s ck4 p16/ad14/ s ot4 p15/ad1 3 / s in4 x1 v ss vcc p14/ad12/ s ck 3 p1 3 /ad11/ s ot 3 p12/ad10/ s in 3 /int11r p11/ad09/tot1 p10/ad0 8 /tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int1 3 x0 p75/an21/int5 p74/an20/int4 p7 3 /an19/int 3 p72/an1 8 /int2 p71/an17/int1 p70/an16/int0 v ss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg 8 (9) p6 3 /an 3 /ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2( 3 ) p60/an0/ppg0(1) av ss avrl avrh avcc p57/an15/da01 p00/ad00/int 8 pa1/tx0 pa0/rx0/int 8 r p97/out 3 p96/out2 p95/out1 p94/out0 p9 3 /ppg7(6) p92/ppg5(4) p91/ppg 3 (2) p90/ppg1(0) v ss vcc p 8 7/ s ck1 p 8 6/ s ot1 p 8 5/ s in1 p 8 4/ s ck0/int15r p 83 / s ot0/tot2 p 8 2/ s in0/tin2/int14r p 8 1/tot0/ckot/int1 3 r p 8 0/tin0/adtg/int12r p77/an2 3 /int7 p76/an22/int6 md0 p26/a22/in2 p27/a2 3 /in 3 p 3 0/ale/in4 p 3 4/hrq/out4 p5 3 /an11/tin 3 p52/an10/ s ck2 p51/an9/ s ot2 p50/an 8 / s in2 p47/ s cl1 p46/ s da1 p45/ s cl0/frck1 p44/ s da0/frck0 p4 3 /in7/tx1 p42/in6/rx1/int9r c v ss vcc p41/x1a * p40/x0a * p 3 7/clk/out7 p 3 6/rdy/out6 lqfp - 100 99 p24/a20/in0 100 p25/a21/in1 2 8 p56/an14/da00 27 p55/an1 3 26 p54/an12/tot 3 49 md2 50 md1 7 8 p0 3 /ad0 3 /int11 77 p02/ad02/int10 76 p01/ad01/int9 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 5 8 59 55 56 57 54 5 3 52 51 12 3 4567 8 9 1011121 3 14 15 16 1 8 17 21 20 19 22 2 3 24 25 r s t p 3 1/rd/in5 p 3 2/wrl/wr/rx2/int10r p 33 /wrh/tx2 p 3 5/hak/out5 mb90860e series 8 mb90867e(s)/mb90f867e(s) (continued) (top view) ( fpt - 100p - m06 ) 100 99 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 p04/ad04/int12 p2 3 /a19/ppgf(e) p22/a1 8 /ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9( 8 ) p17/ad15 p16/ad14 p15/ad1 3 x1 v ss vcc p14/ad12/ s ck 3 p1 3 /ad11/ s ot 3 p12/ad10/ s in 3 /int11r p11/ad09/tot1 p10/ad0 8 /tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int1 3 x0 p75/an21/int5 p0 3 /ad0 3 /int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int 8 pa1 pa0/int 8 r p97/out 3 p96/out2 p95/out1 p94/out0 p9 3 /ppg7(6) p92/ppg5(4) p91/ppg 3 (2) p90/ppg1(0) v ss vcc p 8 7/ s ck1 p 8 6/ s ot1 p 8 5/ s in1 p 8 4/ s ck0/int15r p 83 / s ot0/tot2 p 8 2/ s in0/tin2/int14r p 8 1/tot0/ckot/int1 3 r p 8 0/tin0/adtg/int12r p77/an2 3 /int7 p76/an22/int6 md0 md1 md2 p24/a20/in0 p25/a21/in1 p26/a22/in2 p27/a2 3 /in 3 p 3 0/ale/in4 p 3 4/hrq/out4 p56/an14 p55/an1 3 p54/an12/tot 3 p5 3 /an11/tin 3 p52/an10/ s ck2 p51/an9/ s ot2 p50/an 8 / s in2 p47/ s cl1 p46/ s da1 p45/ s cl0/frck1 p44/ s da0/frck0 p4 3 /in7 p42/in6/int9r c v ss vcc p41/x1a * p40/x0a * p 3 7/clk/out7 p 3 6/rdy/out6 qfp - 100 8 0797 8 77 76 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 12 3 4567 8 9 1011121 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 p74/an20/int4 p7 3 /an19/int 3 p72/an1 8 /int2 p71/an17/int1 p70/an16/int0 p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg 8 (9) p61/an1/ppg2( 3 ) av ss p57/an15 avcc p60/an0/ppg0(1) avrl avrh v ss p62/an2/ppg4(5) p6 3 /an 3 /ppg6(7) r s t p 3 1/rd/in5 p 33 /wrh p 3 5/hak/out5 p 3 2/wrl/wr/int10r * : x0a, x1a : mb90867e, mb90f867e p40, p41 : mb90867es/mb90f867es mb90860e series 9 (continued) (top view) (fpt-100p-m05) 9 8 97 96 95 94 9 3 92 91 90 8 9 88 8 7 8 6 8 5 8 4 83 8 2 8 1 8 0 79 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 p04/ad04/int12 p2 3 /a19/ppgf(e) p22/a1 8 /ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9( 8 ) p17/ad15 p16/ad14 p15/ad1 3 x1 v ss vcc p14/ad12/ s ck 3 p1 3 /ad11/ s ot 3 p12/ad10/ s in 3 /int11r p11/ad09/tot1 p10/ad0 8 /tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int1 3 x0 p00/ad00/int 8 pa1 pa0/int 8 r p97/out 3 p96/out2 p95/out1 p94/out0 p9 3 /ppg7(6) p92/ppg5(4) p91/ppg 3 (2) p90/ppg1(0) v ss vcc p 8 7/ s ck1 p 8 6/ s ot1 p 8 5/ s in1 p 8 4/ s ck0/int15r p 83 / s ot0/tot2 p 8 2/ s in0/tin2/int14r p 8 1/tot0/ckot/int1 3 r p 8 0/tin0/adtg/int12r p77/an2 3 /int7 p76/an22/int6 md0 p26/a22/in2 p27/a2 3 /in 3 p 3 0/ale/in4 p 3 4/hrq/out4 p5 3 /an11/tin 3 p52/an10/ s ck2 p51/an9/ s ot2 p50/an 8 / s in2 p47/ s cl1 p46/ s da1 p45/ s cl0/frck1 p44/ s da0/frck0 p4 3 /in7 p42/in6/int9r c v ss vcc p41/x1a * p40/x0a * p 3 7/clk/out7 p 3 6/rdy/out6 99 p24/a20/in0 100 p25/a21/in1 2 8 p56/an14 27 p55/an1 3 26 p54/an12/tot 3 49 md2 50 md1 7 8 p0 3 /ad0 3 /int11 77 p02/ad02/int10 76 p01/ad01/int9 lqfp - 100 75 74 7 3 72 71 70 69 6 8 67 66 65 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 12 3 4567 8 9 1011121 3 14 15 16 17 1 8 19 20 21 22 2 3 24 25 p75/an21/int5 p74/an20/int4 p7 3 /an19/int 3 p72/an1 8 /int2 p71/an17/int1 p70/an16/int0 v ss p67/an7/ppge(f) p66/an6/ppgc(d) p65/an5/ppga(b) p64/an4/ppg 8 (9) p6 3 /an 3 /ppg6(7) p62/an2/ppg4(5) p61/an1/ppg2( 3 ) p60/an0/ppg0(1) av ss avrl avrh avcc p57/an15 r s t p 3 1/rd/in5 p 33 /wrh p 3 5/hak/out5 p 3 2/wrl/wr/int10r * : x0a, x1a : mb90867e, mb90f867e p40, p41 : mb90867es, mb90f867es mb90860e series 10 pin description (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 1 to 4 99 to 2 p24 to p27 g general purpose i/o pins. the r egister can be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a20 to a23 output pins of the external address bus. when the corresponding bit in the external address output co ntrol register (hacr) is 0, the pins are enabled as high addre ss output pins (a20 to a23). in0 to in3 trigger input pins for input captures 0 to 3. 53 p30 g general purpose i/o pin.the register can be set to select whether to use a pull-up resistor.this f unction is enabled in single-chip mode. ale address latch enable output pin. this function is enabled when the external bus is enabled. in4 trigger input pin for input capture 4. 64 p31 g general purpose i/o pin.the register can be set to select whether to use a pull-up resistor.this f unction is enabled in single-chip mode. rd external read strobe output pin. th is function is enabled when the external bus is enabled. in5 trigger input pin for input capture 5. 75 p32 g general purpose i/o pin. the regist er can be set to select whether to use a pull-up resistor. this func tion is enabled either in single- chip mode or with the wr /wrl pin output disabled. wr / wrl write strobe output pin for the external data bus. this function is enabled when both the external bus and the wr /wrl pin output are enabled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access while wr is used to write-strobe 8 bits of the data bus in 8-bit access. int10r external interrupt request input pin (sub) . 86 p33 g general purpose i/o pin. the regist er can be set to select whether to use a pull-up resistor.this function is enabled either in single- chip mode or with the wrh pin output disabled. wrh write strobe output pin for the 8 higher bits of the external data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mo de is selected, and when the wrh output pin is enabled. mb90860e series 11 (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 97 p34 g general purpose i/o pin. the r egister can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hrq hold request input pin. this f unction is enabled when both the external bus and the hol d function are enabled. out4 waveform output pin for output compare 4. 10 8 p35 g general purpose i/o pin. the r egister can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compare 5. 11 9 p36 g general purpose i/o pin. the r egister can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the ex ternal ready function disabled. rdy external ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compare 6. 12 10 p37 g general purpose i/o pin. the r egister can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the clock output disabled. clk clock output pin. this function is enabled when both the external bus and clock output are enabled. out7 waveform output pin for output compare 7. 13, 14 11, 12 p40, p41 f general purpose i/o pins. (devices with s-suffix) x0a , x1a b input pins for sub-clock (devices without s-suffix) 15 13 v cc ? power (3.5 v to 5.5 v) input pin 16 14 v ss ? gnd pin 17 15 c k this is the power supply stabiliz ation capacitor pin. it should be connected to a higher than or equal to 0.1 f ceramic capacitor. 18 16 p42 f general purpose i/o pin. in6 trigger input pin for input capture 6. int9r external interrupt request input pin (sub) mb90860e series 12 (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 19 17 p43 f general purpose i/o pin. in7 trigger input pin for input capture 7. 20 18 p44 h general purpose i/o pin. sda0 serial data i/o pin for i 2 c 0 frck0 input pin for the 16-bit i/o timer 0 21 19 p45 h general purpose i/o pin. scl0 serial clock i/o pin for i 2 c 0 frck1 input pin for the 16-bit i/o timer 22 20 p46 h general purpose i/o pin. sda1 serial data i/o pin for i 2 c 1 23 21 p47 h general purpose i/o pin. scl1 serial clock i/o pin for i 2 c 1 24 22 p50 o general purpose i/o pin. an8 analog input pin for the a/d converter sin2 serial data input pin for uart2 25 23 p51 i general purpose i/o pin. an9 analog input pin for the a/d converter sot2 serial data output pin for uart2 26 24 p52 i general purpose i/o pin. an10 analog input pin for the a/d converter sck2 clock i/o pin for uart2 27 25 p53 i general purpose i/o pin. an11 analog input pin for the a/d converter tin3 event input pin for the reload timer 3 28 26 p54 i general purpose i/o pin. an12 analog input pin for the a/d converter tot3 output pin for the reload timer 3 29 27 p55 i general purpose i/o pin. an13 analog input pin for the a/d converter 30, 31 28, 29 p56, p57 j general purpose i/o pins. an14, an15 analog input pin for the a/d converter 32 30 av cc k power input pin for the a/d converter analog mb90860e series 13 (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 33 31 avrh l reference voltage input pin for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 34 32 avrl k lower reference voltage input pin for the a/d converter 35 33 av ss k gnd pin for the a/d converter analog 36 to 43 34 to 41 p60 to p67 i general purpose i/o pins. an0 to an7 analog input pins for the a/d converter ppg0, 2, 4, 6, 8, a, c, e output pins for ppgs 44 42 v ss ? gnd pin 45 to 50 43 to 48 p70 to p75 i general purpose i/o pins. an16 to an21 analog input pins for the a/d converter int0 to int5 external interrupt request input pins 51 49 md2 d input pin for specifying the operating mode. 52, 53 50, 51 md1, md0 c input pins for specifying the operating mode. 54 52 rst e reset input 55, 56 53, 54 p76, p77 i general purpose i/o pins. an22, an23 analog input pins for the a/d converter int6, int7 external interrupt request input pins 57 55 p80 f general purpose i/o pin. tin0 event input pin for the reload timer 0 adtg trigger input pin for the a/d converter int12r external interrupt request input pin (sub) 58 56 p81 f general purpose i/o pin. tot0 output pin for the reload timer 0 ckot output pin for the clock monitor int13r external interrupt request input pin (sub) 59 57 p82 m general purpose i/o pin. sin0 serial data input pin for uart0 tin2 event input pin for the reload timer 2 int14r external interrupt request input pin (sub) 60 58 p83 f general purpose i/o pin. sot0 serial data output pin for uart0 tot2 output pin for the reload timer 2 61 59 p84 f general purpose i/o pin. sck0 clock i/o pin for uart0 int15r external interrupt request input pin (sub) mb90860e series 14 (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 62 60 p85 m general purpose i/o pin. sin1 serial data input pin for uart1 63 61 p86 f general purpose i/o pin. sot1 serial data output pin for uart1 64 62 p87 f general purpose i/o pin. sck1 clock i/o pin for uart1 65 63 v cc ? power (3.5 v to 5.5 v) input pins 66 64 v ss ? gnd pins 67 to 70 65 to 68 p90 to p93 f general purpose i/o pin ppg1, 3, 5, 7 output pins for ppgs 71 to 74 69 to 72 p94 to p97 f general purpose i/o pin out0 to out3 waveform output pins for output compares 0 to 3. this function is enabled when the ocu enables waveform output. 75 73 pa0 f general purpose i/o pin. int8r external interrupt request input pin (sub) 76 74 pa1 f general purpose i/o pin. 77 to 84 75 to 82 p00 to p07 g general purpose i/o pins. the r egister can be set to select whether to use a pull-up resist or. this function is enabled in single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of t he external address/data bus. this function is enabled when the external bus is enabled. int8 to int15 external interrupt request input pins. 85 83 p10 g general purpose i/o pin. the register can be set to select whether to use a pull-up resist or. this function is enabled in single-chip mode. ad08 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. tin1 event input pin for the reload timer 1 86 84 p11 g general purpose i/o pin. the register can be set to select whether to use a pull-up resist or. this function is enabled in single-chip mode. ad09 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. tot1 output pin for the reload timer 1 mb90860e series 15 (continued) pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 87 85 p12 n general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. sin3 serial data input pin for uart3 int11r external interrupt request input pin (sub) 88 86 p13 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. sot3 serial data output pin for uart3 89 87 p14 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. sck3 clock i/o pin for uart3 90 88 v cc ? power (3.5 v to 5.5 v) input pin 91 89 v ss ? gnd pin 92 90 x1 a main clock output pin 93 91 x0 main clock input pin 94 92 p15 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. 95 93 p16 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. 96 94 p17 g general purpose i/o pin. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 i/o pin for the external address/data bus. this function is enabled when the external bus is enabled. mb90860e series 16 (continued) *1 : fpt-100p-m06 *2 : fpt-100p-m05 *3 : for the i/o circuit type, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* 3 function qfp100* 1 lqfp100* 2 97 to 100 95 to 98 p20 to p23 g general purpose i/o pins. the register can be set to select whether to use a pull-up resistor.in external bus mode, the pin is enabled as a general-purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins of the external address bus. when the corresponding bit in the external address output control register (hacr) is 0, the pi ns are enabled as high address output pins (a16 to a19). ppg9,ppgb, ppgd,ppgf output pins for ppgs mb90860e series 17 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit low-speed oscillation feedback resistor = approx. 10 m ? c mask rom and evaluation device: cmos hysteresis input pin flash device: cmos input pin d mask rom and evaluation device: cmos hysteresis input pin pull-down resistor value: approx. 50 k ? flash memory device: cmos input pin no pull-down e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? standby control signal x1 x0 xout standby control signal x1a x0a xout hy s tere s i s inp u t s r p u ll-down re s i s tor hy s tere s i s inp u t s r p u ll- u p re s i s tor hy s tere s i s inp u t s r mb90860e series 18 (continued) type circuit remarks f cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with the standby- time input shutdown function) automotive input (with the standby-time input shutdown function) g cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with the standby- time input shutdown function) automotive input (with the standby-time input shutdown function) ttl input (with the standby-time input shutdown function) programmable pull-up resistor: 50 k ? approx. h cmos level output (i ol = 3 ma, i oh = ? 3 ma) cmos hysteresis inputs (with the standby- time input shutdown function) automotive input (with the standby-time input shutdown function) hy s tere s i s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown po u t no u t r p-ch n-ch p u ll- u p control hy s tere s i s inp u t s a u tomotive inp u t s ttl inp u t s t a nd b y control for inp u t s h u tdown po u t no u t r n-ch p-ch p-ch hy s tere s i s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown po u t no u t r p-ch n-ch mb90860e series 19 (continued) type circuit remarks i cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis inputs (with the standby- time input shutdown function) automotive input (with the standby-time in- put shutdown function) a/d converter analog input j cmos level output (i ol = 4 ma, i oh = ? 4 ma) d/a analog output cmos hysteresis inputs (with the standby- time input shutdown function) automotive input (with the standby-time in- put shutdown function) a/d converter analog input k power supply input protection circuit l a/d converter reference voltage power supply input pin, with the protection circuit flash devices do not have a protection circuit against v cc for pin avrh hy s tere s i s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown an a log inp u t po u t no u t r n-ch p-ch hy s tere s i s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown an a log inp u t an a log o u tp u t po u t no u t r p-ch n-ch p-ch n-ch ane avr ane p-ch n-ch mb90860e series 20 (continued) type circuit remarks m cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos inputs (with the standby-time input shutdown function) automotive input (with the standby-time input shutdown function) n cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos inputs (with the standby-time input shutdown function) automotive input (with the standby-time input shutdown function) ttl input (with the standby-time input shutdown function) programmable pull-up registor:50 k ? approx o cmos level output(i ol = 4 ma, i oh = ? 4 ma) cmos inputs (with the standby-time input shutdown function) automotive input (with the standby-time input shutdown function) a/d converter analog input cmo s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown po u t no u t r p-ch n-ch p u ll- u p control cmo s inp u t s a u tomotive inp u t s ttl inp u t s t a nd b y control for inp u t s h u tdown po u t no u t r p-ch n-ch p-ch cmo s inp u t s a u tomotive inp u t s s t a nd b y control for inp u t s h u tdown an a log inp u t po u t no u t r p-ch n-ch mb90860e series 21 handling devices 1. preventing latch-up cmos ic may suffer latch-up u nder the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the ra ted voltage is applied between v cc and v ss pins. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. handling unused pins leaving unused input pins open may result in misbehav ior or latch up and possib le permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output st ate and can be left open, or the input state with the above described connection. 3. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss to the device from the current supply source at a low impedance. as a measure against power supply noi se, connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss in the vicinity of v cc and v ss pins of the device 4. mode pin (md0 to md2) connect the mode pin directly to v cc or v ss pins. to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to v cc or v ss pins and to provide a low-impedance connection. vcc vss vss vcc vss vcc mb90860e series vcc vss vcc vss mb90860e series 22 5. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an23) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d conv erter supply and analog inputs. in this case, make sure that the voltage not exceed avrh or av cc (turning on/off the analog and digi tal power supplies simultaneously is acceptable) . 6. connection of unused pins of a/d converter if a/d converter is used connect unused pins of a/d converter to av cc = v cc , av ss = avrh = avrl = v ss . 7. crystal oscillator circuit x0, x1 pins and x0a, x1a pins may be possible causes of abnormal oper ations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. it is highly recommended to provide a printed circuit bo ard art work surrounding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. 8. pull-up/down resistors the mb90860e series does not support inte rnal pull-up/down resistors (port 0 to port 3: built-in pull-up resistors). use external components where needed. 9. using external clock to use external clock, drive the x0 pin and leave x1 pin open. 10. precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillat or, use pull-down handling on the x0a pin, and leave the x1a pin open. 11. notes on during operation of pll clock mode if the pll clock mode is selected, the mb90860 series atte mpt to be working with the self-oscillating circuit even when there is no external oscillator or external clock in put is stopped. performance of this operation, however, cannot be guaranteed. 12. notes on energization to prevent the internal regulator circ uit from malfunctioning, set the volta ge rise time during energization at 50 or more s (0.2 v to 2.7 v) x0 x1 mb90860e series open mb90860e series 23 13. stabilization of power supply voltage a sudden change in the supply voltage may cause the de vice to malfunction even within the specified v cc supply voltage operating range. therefore, the v cc supply voltage should be stabilized. for the reference, stabilize the supply voltage by setting the following value. v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz/60 hz) fall below 10 % of the standard v cc supply voltage the coefficient of fluctuation does not ex ceed 0.1 v/ms at instantaneous power switching. 14. initialization in the device, there are internal registers which are initializ ed only by a power-on reset. to initialize these registers, turn on the power again. 15. port 0 to port 3 output during power-on (external-bus mode) as shown below, when power is turned on in external-bus mode, in spite of reset input, there is a possibility that output signal of port 0 to port 3 might be unstable. 16. flash security function the security bit is located in the area of the flash memory. if protection code 01 h is written in the security bit, the flash me mory is in the protected state by security. therefore please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security bit. flash memory size address for security bit mb90f867e(s) embedded 1 mbit flash memory fe0001 h port 0 to port 3 o u tp u t s might b e u n s t ab le port 0 to port 3 o u tp u t s = hi-z port 0 to port 3 v cc 1/2v cc mb90860e series 24 block diagrams mb90v340e-101/102 ram uart prescaler 8/10-bit 24 channels 16-bit reload timer i/o timer 0 clock controller input capture 8 channels output compare 8 channels can controller external interrupt 16lx cpu f 2 mc-16 bus x0,x1 rst sot4 to sot0 sck4 to sck0 sin4 to sin0 avcc avss an23 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 rx2 to rx0 tx2 to tx0 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wr /wrl wrh hrq hak rdy clk x0a,x1a* 5 channels 10-bit dac 2 channels da01, da00 i/o timer 1 frck0 frck1 8/16-bit ppg 16 channels ppgf to ppg0 i 2 c interface sda1, sda0 scl1, scl0 3 channels 5 channels 2 channels dmac * : only for mb90v340e-102 clock monitor ckot (int15r to int8r) int7 to int0 adc 16 channels 30 kbytes 4 channels mb90860e series 25 mb90867e(s), mb90f867e(s) ram rom/flash uart prescaler 8/10-bit 24 channels 16-bit reload timer i/o timer 0 clock controller input capture 8 channels output compare 8 channels external interrupt 16lx cpu f 2 mc-16 bus x0,x1 rst sot3 to sot0 sck3 to sck0 sin3 to sin0 avcc avss an15 to an0 avrh avrl adtg tin3 to tin0 tot3 to tot0 in7 to in0 out7 to out0 int15 to int8 external bus interface ad15 to ad00 a23 to a16 ale rd wr /wrl wrh hrq hak rdy clk x0a,x1a* 128 kbytes 4 channels i/o timer 1 frck0 frck1 8/16-bit ppg 16 channels ppgf to ppg0 4 channels i 2 c interface sda1, sda0 scl1, scl0 2 channels an23 to an16 6 kbytes dmac * : only for devices without ?s? suffix clock monitor ckot (int15r to int8r) int7 to int0 adc 16 channels 4 channels mb90860e series 26 memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, an d its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. mb90v 3 40e-101/102 ffffff h ff0000 h feffff h fe0000 h fdffff h fd0000 h fcffff h fc0000 h fbffff h fb0000 h faffff h fa0000 h f9ffff h f90000 h f 8 ffff h f 8 0000 h 00ffff h 00 8 000 h 007fff h 007900 h 007 8 ff h 000100 h 0000ef h 000000 h rom (ff ba nk) rom (fe ba nk) rom (fd ba nk) rom (fc ba nk) rom (fb ba nk) rom (fa ba nk) rom (f9 ba nk) rom (f 8 ba nk) rom (im a ge of ff ba nk) peripher a l ram 3 0 k b yte s peripher a l extern a l a cce ss a re a : no a cce ss mb90 8 67e( s ) mb90f 8 67e( s ) ffffff h ff0000 h feffff h fe0000 h 0000ef h 000000 h 00ffff h 007fff h 007900 h 00 3 fff h 000100 h 00 8 000 h extern a l a cce ss a re a rom (im a ge of ff ba nk) peripher a l ram 6 k b yte s extern a l a cce ss a re a peripher a l rom (ff ba nk) rom (fe ba nk) extern a l a cce ss a re a mb90860e series 27 i/o map (continued) address register abbrevia- tion access resource name initial value 000000 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 000001 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 000002 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 000003 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 000004 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 000005 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 000006 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 000007 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 000008 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 000009 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 00000a h port a data register pdra r/w port a xxxxxxxx b 00000b h port 5 analog input enable regi ster ader5 r/w port 5, a/d 11111111 b 00000c h port 6 analog input enable regi ster ader6 r/w port 6, a/d 11111111 b 00000d h port 7 analog input enable regi ster ader7 r/w port 7, a/d 11111111 b 00000e h input level select register 0 ilsr0 r/w ports xxxxxxxx b 00000f h input level select register 1 ilsr1 r/w ports xxxx0xxx b 000010 h port 0 direction register ddr0 r/w port 0 00000000 b 000011 h port 1 direction register ddr1 r/w port 1 00000000 b 000012 h port 2 direction register ddr2 r/w port 2 00000000 b 000013 h port 3 direction register ddr3 r/w port 3 00000000 b 000014 h port 4 direction register ddr4 r/w port 4 00000000 b 000015 h port 5 direction register ddr5 r/w port 5 00000000 b 000016 h port 6 direction register ddr6 r/w port 6 00000000 b 000017 h port 7 direction register ddr7 r/w port 7 00000000 b 000018 h port 8 direction register ddr8 r/w port 8 00000000 b 000019 h port 9 direction register ddr9 r/w port 9 00000000 b 00001a h port a direction register ddra r/w port a 00000100 b 00001b h reserved 00001c h port 0 pull-up control register pucr0 r/w port 0 00000000 b 00001d h port 1 pull-up control register pucr1 r/w port 1 00000000 b 00001e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 00001f h port 3 pull-up control register pucr3 w, r/w port 3 00000000 b mb90860e series 28 (continued) address register abbrevia- tion access resource name initial value 000020 h serial mode register 0 smr0 w,r/w uart0 00000000 b 000021 h serial control register 0 scr0 w,r/w 00000000 b 000022 h reception/transmission data register 0 rdr0/ tdr0 r/w 00000000 b 000023 h serial status register 0 ssr0 r,r/w 00001000 b 000024 h extended communication control register 0 eccr0 r,w, r/w 000000xx b 000025 h extended status/control register 0 escr0 r/w 00000100 b 000026 h baud rate generator regi ster 00 bgr00 r/w 00000000 b 000027 h baud rate generator regi ster 01 bgr01 r/w 00000000 b 000028 h serial mode register 1 smr1 w,r/w uart1 00000000 b 000029 h serial control register 1 scr1 w,r/w 00000000 b 00002a h reception/transmission data register 1 rdr1/ tdr1 r/w 00000000 b 00002b h serial status register 1 ssr1 r,r/w 00001000 b 00002c h extended communication control register 1 eccr1 r,w, r/w 000000xx b 00002d h extended status/control register 1 escr1 r/w 00000100 b 00002e h baud rate generator regi ster 10 bgr10 r/w 00000000 b 00002f h baud rate generator regi ster 11 bgr11 r/w 00000000 b 000030 h ppg 0 operation mode control register ppgc0 w,r/w 16-bit ppg 0/1 0x000xx1 b 000031 h ppg 1 operation mode control register ppgc1 w,r/w 0x000001 b 000032 h ppg 0/ppg 1 count clock select register ppg01 r/w 000000x0 b 000033 h reserved 000034 h ppg 2 operation mode control register ppgc2 w,r/w 16-bit ppg 2/3 0x000xx1 b 000035 h ppg 3 operation mode control register ppgc3 w,r/w 0x000001 b 000036 h ppg 2/ppg 3 count clock select register ppg23 r/w 000000x0 b 000037 h reserved 000038 h ppg 4 operation mode control register ppgc4 w,r/w 16-bit ppg 4/5 0x000xx1 b 000039 h ppg 5 operation mode control register ppgc5 w,r/w 0x000001 b 00003a h ppg 4/ppg 5 clock select register ppg45 r/w 000000x0 b 00003b h address detect control register 1 pacsr1 r/w address match detection 1 00000000 b 00003c h ppg 6 operation mode control register ppgc6 w,r/w 16-bit ppg 6/7 0x000xx1 b 00003d h ppg 7 operation mode control register ppgc7 w,r/w 0x000001 b 00003e h ppg 6/ppg 7 count clock control register ppg67 r/w 000000x0 b 00003f h reserved mb90860e series 29 (continued) address register abbrevia- tion access resource name initial value 000040 h ppg 8 operation mode control register ppgc8 w,r/w 16-bit ppg 8/9 0x000xx1 b 000041 h ppg 9 operation mode control register ppgc9 w,r/w 0x000001 b 000042 h ppg 8/ppg 9 count clock control register ppg89 r/w 000000x0 b 000043 h reserved 000044 h ppg a operation mode control register ppgca w,r/w 16-bit ppg a/b 0x000xx1 b 000045 h ppg b operation mode control register ppgcb w,r/w 0x000001 b 000046 h ppg a/ppg b count clock select register ppgab r/w 000000x0 b 000047 h reserved 000048 h ppg c operation mode control register ppgcc w,r/w 16-bit ppg c/d 0x000xx1 b 000049 h ppg d operation mode control register ppgcd w,r/w 0x000001 b 00004a h ppg c/ppg d count clock select register ppgcd r/w 000000x0 b 00004b h reserved 00004c h ppg e operation mode control register ppgce w,r/w 16-bit ppg e/f 0x000xx1 b 00004d h ppg f operation mode contro l register ppgcf w,r/w 0x000001 b 00004e h ppg e/ppg f count clock select register ppgef r/w 000000x0 b 00004f h reserved 000050 h input capture control status 0/1 ics01 r/w input capture 0/1 00000000 b 000051 h input capture edge 0/1 ice01 r/w, r xxx0x0xx b 000052 h input capture control status 2/3 ics23 r/w input capture 2/3 00000000 b 000053 h input capture edge 2/3 ice23 r xxxxxxxx b 000054 h input capture control status 4/5 ics45 r/w input capture 4/5 00000000 b 000055 h input capture edge 4/5 ice45 r xxxxxxxx b 000056 h input capture control status 6/7 ics67 r/w input capture 6/7 00000000 b 000057 h input capture edge 6/7 ice67 r/w, r xxx000xx b 000058 h output compare control status 0 ocs0 r/w output compare 0/1 0000xx00 b 000059 h output compare control status 1 ocs1 r/w 0xx00000 b 00005a h output compare control status 2 ocs2 r/w output compare 2/3 0000xx00 b 00005b h output compare control status 3 ocs3 r/w 0xx00000 b 00005c h output compare control status 4 ocs4 r/w output compare 4/5 0000xx00 b 00005d h output compare control status 5 ocs5 r/w 0xx00000 b 00005e h output compare control status 6 ocs6 r/w output compare 6/7 0000xx00 b 00005f h output compare control status 7 ocs7 r/w 0xx00000 b mb90860e series 30 (continued) address register abbrevia- tion access resource name initial value 000060 h timer control status 0 tmcsr0 r/w 16-bit reload timer 0 00000000 b 000061 h timer control status 0 tmcsr0 r/w xxxx0000 b 000062 h timer control status 1 tmcsr1 r/w 16-bit reload timer 1 00000000 b 000063 h timer control status 1 tmcsr1 r/w xxxx0000 b 000064 h timer control status 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 000065 h timer control status 2 tmcsr2 r/w xxxx0000 b 000066 h timer control status 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 000067 h timer control status 3 tmcsr3 r/w xxxx0000 b 000068 h a/d control status 0 adcs0 r/w a/d converter 000xxxx0 b 000069 h a/d control status 1 adcs1 r/w 0000000x b 00006a h a/d data 0 adcr0 r 00000000 b 00006b h a/d data 1 adcr1 r xxxxxx00 b 00006c h adc setting 0 adsr0 r/w 00000000 b 00006d h adc setting 1 adsr1 r/w 00000000 b 00006e h reserved 00006f h rom mirror function select romm w rom mirror xxxxxxx1 b 000070 h to 00009a h reserved 00009b h dma descriptor channel specified register dcsr r/w dma 00000000 b 00009c h dma status l register dsrl r/w 00000000 b 00009d h dma status h register dsrh r/w 00000000 b 00009e h address detect control register 0 pacsr0 r/w address match detection 0 00000000 b 00009f h delayed interrupt/release dirr r/w delayed interrupt xxxxxxx0 b 0000a0 h low-power mode control register lpmcr w,r/w low power control circuit 00011000 b 0000a1 h clock selection register ckscr r,r/w low power control circuit 11111100 b 0000a2 h , 0000a3 h reserved 0000a4 h dma stop status register dssr r/w dma 00000000 b 0000a5 h automatic ready function select register arsr w external memory access 0011xx00 b 0000a6 h external address output control register hacr w 00000000 b 0000a7 h bus control signal select ion register ecsr w 0000000x b 0000a8 h watchdog control register wdtc r,w watchdog timer xxxxx111 b mb90860e series 31 (continued) address register abbrevia- tion access resource name initial value 0000a9 h time base timer control register tbtc w,r/w time base timer 1xx00100 b 0000aa h watch timer control register wtc r,r/w watch timer 1x001000 b 0000ab h reserved 0000ac h dma enable l register derl r/w dma 00000000 b 0000ad h dma enable h register derh r/w 00000000 b 0000ae h flash control status register (flash devices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 b 0000af h reserved 0000b0 h interrupt control register 00 icr00 w,r/w interrupt control 00000111 b 0000b1 h interrupt control register 01 icr01 w,r/w 00000111 b 0000b2 h interrupt control register 02 icr02 w,r/w 00000111 b 0000b3 h interrupt control register 03 icr03 w,r/w 00000111 b 0000b4 h interrupt control register 04 icr04 w,r/w 00000111 b 0000b5 h interrupt control register 05 icr05 w,r/w 00000111 b 0000b6 h interrupt control register 06 icr06 w,r/w 00000111 b 0000b7 h interrupt control register 07 icr07 w,r/w 00000111 b 0000b8 h interrupt control register 08 icr08 w,r/w 00000111 b 0000b9 h interrupt control register 09 icr09 w,r/w 00000111 b 0000ba h interrupt control register 10 icr10 w,r/w 00000111 b 0000bb h interrupt control register 11 icr11 w,r/w 00000111 b 0000bc h interrupt control register 12 icr12 w,r/w 00000111 b 0000bd h interrupt control register 13 icr13 w,r/w 00000111 b 0000be h interrupt control register 14 icr14 w,r/w 00000111 b 0000bf h interrupt control register 15 icr15 w,r/w 00000111 b 0000c0 h d/a converter data 0 register dat0 r/w d/a converter xxxxxxxx b 0000c1 h d/a converter data 1 register dat1 r/w xxxxxxxx b 0000c2 h d/a control 0 register dacr0 r/w xxxxxxx0 b 0000c3 h d/a control 1 register dacr1 r/w xxxxxxx0 b 0000c4 h , 0000c5 h reserved 0000c6 h external interrupt enable 0 enir0 r/w external interrupt 0 00000000 b 0000c7 h external interrupt source 0 eirr0 r/w xxxxxxxx b 0000c8 h external interrupt level setting 0 elvr0 r/w 00000000 b 0000c9 h external interrupt level setting 0 elvr0 r/w 00000000 b mb90860e series 32 (continued) address register abbrevia- tion access resource name initial value 0000ca h external interrupt enable 1 enir1 r/w external interrupt 1 00000000 b 0000cb h external interrupt source 1 eirr1 r/w xxxxxxxx b 0000cc h external interrupt level setting 1 elvr1 r/w 00000000 b 0000cd h external interrupt level setting 1 elvr1 r/w 00000000 b 0000ce h external interrupt source select eissr r/w 00000000 b 0000cf h pll/sub clock control register psccr w pll xxxx0000 b 0000d0 h dma buffer address po inter l register bapl r/w dma xxxxxxxx b 0000d1 h dma buffer address pointe r m register bapm r/w xxxxxxxx b 0000d2 h dma buffer address pointe r h register baph r/w xxxxxxxx b 0000d3 h dma control register dmacs r/w xxxxxxxx b 0000d4 h i/o register address pointer l register ioal r/w xxxxxxxx b 0000d5 h i/o register address pointer h register ioah r/w xxxxxxxx b 0000d6 h data counter l register dctl r/w xxxxxxxx b 0000d7 h data counter h register dcth r/w xxxxxxxx b 0000d8 h serial mode register 2 smr2 w,r/w uart2 00000000 b 0000d9 h serial control register 2 scr2 w,r/w 00000000 b 0000da h reception/transmission data register 2 rdr2/ tdr2 r/w 00000000 b 0000db h serial status register 2 ssr2 r,r/w 00001000 b 0000dc h extended communication control register 2 eccr2 r,w, r/w 000000xx b 0000dd h extended status control r egister 2 escr2 r/w 00000100 b 0000de h baud rate generator register 20 bgr20 r/w 00000000 b 0000df h baud rate generator register 21 bgr21 r/w 00000000 b 0000e0 h to 0000ff h external area 007900 h reload register l0 prll0 r/w 16-bit ppg 0/1 xxxxxxxx b 007901 h reload register h0 prlh0 r/w xxxxxxxx b 007902 h reload register l1 prll1 r/w xxxxxxxx b 007903 h reload register h1 prlh1 r/w xxxxxxxx b 007904 h reload register l2 prll2 r/w 16-bit ppg 2/3 xxxxxxxx b 007905 h reload register h2 prlh2 r/w xxxxxxxx b 007906 h reload register l3 prll3 r/w xxxxxxxx b 007907 h reload register h3 prlh3 r/w xxxxxxxx b mb90860e series 33 (continued) address register abbrevia- tion access resource name initial value 007908 h reload register l4 prll4 r/w 16-bit ppg 4/5 xxxxxxxx b 007909 h reload register h4 prlh4 r/w xxxxxxxx b 00790a h reload register l5 prll5 r/w xxxxxxxx b 00790b h reload register h5 prlh5 r/w xxxxxxxx b 00790c h reload register l6 prll6 r/w 16-bit ppg 6/7 xxxxxxxx b 00790d h reload register h6 prlh6 r/w xxxxxxxx b 00790e h reload register l7 prll7 r/w xxxxxxxx b 00790f h reload register h7 prlh7 r/w xxxxxxxx b 007910 h reload register l8 prll8 r/w 16-bit ppg 8/9 xxxxxxxx b 007911 h reload register h8 prlh8 r/w xxxxxxxx b 007912 h reload register l9 prll9 r/w xxxxxxxx b 007913 h reload register h9 prlh9 r/w xxxxxxxx b 007914 h reload register la prlla r/w 16-bit ppg a/b xxxxxxxx b 007915 h reload register ha prlha r/w xxxxxxxx b 007916 h reload register lb prllb r/w xxxxxxxx b 007917 h reload register hb prlhb r/w xxxxxxxx b 007918 h reload register lc prllc r/w 16-bit ppg c/d xxxxxxxx b 007919 h reload register hc prlhc r/w xxxxxxxx b 00791a h reload register ld prlld r/w xxxxxxxx b 00791b h reload register hd prlhd r/w xxxxxxxx b 00791c h reload register le prlle r/w 16-bit ppg e/f xxxxxxxx b 00791d h reload register he prlhe r/w xxxxxxxx b 00791e h reload register lf prllf r/w xxxxxxxx b 00791f h reload register hf prlhf r/w xxxxxxxx b 007920 h input capture 0 ipcp0 r input capture 0/1 xxxxxxxx b 007921 h input capture 0 ipcp0 r xxxxxxxx b 007922 h input capture 1 ipcp1 r xxxxxxxx b 007923 h input capture 1 ipcp1 r xxxxxxxx b 007924 h input capture 2 ipcp2 r input capture 2/3 xxxxxxxx b 007925 h input capture 2 ipcp2 r xxxxxxxx b 007926 h input capture 3 ipcp3 r xxxxxxxx b 007927 h input capture 3 ipcp3 r xxxxxxxx b 007928 h input capture 4 ipcp4 r input capture 4/5 xxxxxxxx b 007929 h input capture 4 ipcp4 r xxxxxxxx b 00792a h input capture 5 ipcp5 r xxxxxxxx b 00792b h input capture 5 ipcp5 r xxxxxxxx b mb90860e series 34 (continued) address register abbrevia- tion access resource name initial value 00792c h input capture 6 ipcp6 r input capture 6/7 xxxxxxxx b 00792d h input capture 6 ipcp6 r xxxxxxxx b 00792e h input capture 7 ipcp7 r xxxxxxxx b 00792f h input capture 7 ipcp7 r xxxxxxxx b 007930 h output compare 0 occp0 r/w output compare 0/1 xxxxxxxx b 007931 h output compare 0 occp0 r/w xxxxxxxx b 007932 h output compare 1 occp1 r/w xxxxxxxx b 007933 h output compare 1 occp1 r/w xxxxxxxx b 007934 h output compare 2 occp2 r/w output compare 2/3 xxxxxxxx b 007935 h output compare 2 occp2 r/w xxxxxxxx b 007936 h output compare 3 occp3 r/w xxxxxxxx b 007937 h output compare 3 occp3 r/w xxxxxxxx b 007938 h output compare 4 occp4 r/w output compare 4/5 xxxxxxxx b 007939 h output compare 4 occp4 r/w xxxxxxxx b 00793a h output compare 5 occp5 r/w xxxxxxxx b 00793b h output compare 5 occp5 r/w xxxxxxxx b 00793c h output compare 6 occp6 r/w output compare 6/7 xxxxxxxx b 00793d h output compare 6 occp6 r/w xxxxxxxx b 00793e h output compare 7 occp7 r/w xxxxxxxx b 00793f h output compare 7 occp7 r/w xxxxxxxx b 007940 h timer data 0 tcdt0 r/w i/o timer 0 00000000 b 007941 h timer data 0 tcdt0 r/w 00000000 b 007942 h timer control status 0 tccsl0 r/w 00000000 b 007943 h timer control status 0 tccsh0 r/w 0xxxxxxx b 007944 h timer data 1 tcdt1 r/w i/o timer 1 00000000 b 007945 h timer data 1 tcdt1 r/w 00000000 b 007946 h timer control status 1 tccsl1 r/w 00000000 b 007947 h timer control status 1 tccsh1 r/w 0xxxxxxx b 007948 h timer 0/reload 0 tmr0/ tmrlr0 r/w 16-bit reload timer 0 xxxxxxxx b 007949 h r/w xxxxxxxx b 00794a h timer 1/reload 1 tmr1/ tmrlr1 r/w 16-bit reload timer 1 xxxxxxxx b 00794b h r/w xxxxxxxx b 00794c h timer 2/reload 2 tmr2/ tmrlr2 r/w 16-bit reload timer 2 xxxxxxxx b 00794d h r/w xxxxxxxx b 00794e h timer 3/reload 3 tmr3/ tmrlr3 r/w 16-bit reload timer 3 xxxxxxxx b 00794f h r/w xxxxxxxx b mb90860e series 35 (continued) address register abbrevia- tion access resource name initial value 007950 h serial mode register 3 smr3 w,r/w uart3 00000000 b 007951 h serial control register 3 scr3 w,r/w 00000000 b 007952 h reception/transmission data register 3 rdr3/ tdr3 r/w 00000000 b 007953 h serial status register 3 ssr3 r,r/w 00001000 b 007954 h extended communication control register 3 eccr3 r,w, r/w 000000xx b 007955 h extended status control register escr3 r/w 00000100 b 007956 h baud rate generator register 30 bgr30 r/w 00000000 b 007957 h baud rate generator register 31 bgr31 r/w 00000000 b 007958 h serial mode register 4 smr4 w,r/w uart4 00000000 b 007959 h serial control register 4 scr4 w,r/w 00000000 b 00795a h reception/transmission data register 4 rdr4/ tdr4 r/w 00000000 b 00795b h serial status register 4 ssr4 r,r/w 00001000 b 00795c h extended communication control register 4 eccr4 r,w, r/w 000000xx b 00795d h extended status control register escr4 r/w 00000100 b 00795e h baud rate generator register 40 bgr40 r/w 00000000 b 00795f h baud rate generator register 41 bgr41 r/w 00000000 b 007960 h to 00796b h reserved 00796c h clock output enable register clkr r/w clock monitor xxxx0000 b 00796d h to 00796f h reserved 007970 h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 00000000 b 007971 h i 2 c bus control register 0 ibcr0 w,r/w 00000000 b 007972 h i 2 c 10-bit slave address register 0 itbal0 r/w 00000000 b 007973 h itbah0 r/w 00000000 b 007974 h i 2 c 10-bit slave address mask register 0 itmkl0 r/w 11111111 b 007975 h itmkh0 r/w 00111111 b 007976 h i 2 c 7-bit slave address register 0 isba0 r/w 00000000 b 007977 h i 2 c 7-bit slave address mask register 0 ismk0 r/w 01111111 b 007978 h i 2 c data register 0 idar0 r/w 00000000 b 007979 h , 00797a h reserved mb90860e series 36 (continued) address register abbrevia- tion access resource name initial value 00797b h i 2 c clock control register 0 iccr0 r/w i 2 c interface 0 00011111 b 00797c h to 00797f h reserved 007980 h i 2 c bus status register 1 ibsr1 r i 2 c interface 1 00000000 b 007981 h i 2 c bus control register 1 ibcr1 w,r/w 00000000 b 007982 h i 2 c 10-bit slave address register 1 itbal1 r/w 00000000 b 007983 h itbah1 r/w 00000000 b 007984 h i 2 c 10-bit slave address mask register 1 itmkl1 r/w 11111111 b 007985 h itmkh1 r/w 00111111 b 007986 h i 2 c 7-bit slave address register 1 isba1 r/w 00000000 b 007987 h i 2 c 7-bit slave address mask register 1 ismk1 r/w 01111111 b 007988 h i 2 c data register 1 idar1 r/w 00000000 b 007989 h , 00798a h reserved 00798b h i 2 c clock control register 1 iccr1 r/w i 2 c interface 1 00011111 b 00798c h to 0079c1 h reserved 0079c2 h clock modulator control register (setting prohibited) cmcr r, r/w clock modulator (using prohibited) 0001x000 b 0079c3 h to 0079df h reserved 0079e0 h detect address setting 0 padr0 r/w address match detection 0 xxxxxxxx b 0079e1 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e2 h detect address setting 0 padr0 r/w xxxxxxxx b 0079e3 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e4 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e5 h detect address setting 1 padr1 r/w xxxxxxxx b 0079e6 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e7 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e8 h detect address setting 2 padr2 r/w xxxxxxxx b 0079e9 h to 0079ef h reserved mb90860e series 37 (continued) notes : ? initial value of ?x? represents unknown value. ? any write access to reserved addresses in i/o map s hould not be performed. a read access to reserved addresses results in reading ?x?. address register abbrevia- tion access resource name initial value 0079f0 h detect address setting 3 padr3 r/w address match detection 1 xxxxxxxx b 0079f1 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f2 h detect address setting 3 padr3 r/w xxxxxxxx b 0079f3 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f4 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f5 h detect address setting 4 padr4 r/w xxxxxxxx b 0079f6 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f7 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f8 h detect address setting 5 padr5 r/w xxxxxxxx b 0079f9 h to 007fff h reserved mb90860e series 38 interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? (reserved) n ? #11 ffffd0 h icr00 0000b0 h (reserved) n ? #12 ffffcc h input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h input capture 7 y1 ? #14 ffffc4 h i 2 c0 n ? #15 ffffc0 h icr02 0000b2 h (reserved) n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 0/1/4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 2/3/6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h time base timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 0 to 3, 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 4 to 7, 12 to 15 y1 4 #28 ffff8c h 8/10-bit a/d converter y1 5 #29 ffff88 h icr09 0000b9 h i/o timer 0, i/o timer 1 n ? #30 ffff84 h input capture 4/5, i 2 c1 y1 6 #31 ffff80 h icr10 0000ba h output compare 0/1/4/5 y1 7 #32 ffff7c h input capture 0 to 3 y1 8 #33 ffff78 h icr11 0000bb h output compare 2/3/6/7 y1 9 #34 ffff74 h uart 0 reception y2 10 #35 ffff70 h icr12 0000bc h uart 0 transmission y1 11 #36 ffff6c h uart 1 reception / uart 3 reception y2 12 #37 ffff68 h icr13 0000bd h uart 1 transmission / uart 3 transmission y1 13 #38 ffff64 h mb90860e series 39 (continued) y1 : usable y2 : usable, with ei 2 os stop function n : unusable notes : ? the peripheral resources sharing the icr r egister have the same interrupt level. ? when two peripheral resources share the icr regist er, only one can use extended intelligent i/o service at a time. ? when either of the two peripheral resources shari ng the icr register specifies extended intelligent i/o service, the other one cannot use interrupts. interrupt cause ei 2 os clear dma ch number interrupt vector interrupt control register number address number address uart 2 reception / uart 4 reception y2 14 #39 ffff60 h icr14 0000be h uart 2 transmission / uart 4 transmission y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h mb90860e series 40 electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0 v. *2 : set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3 : v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : applicable to pins : p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p4 7, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa1 (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avrh, avrl v ss ? 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh avrl input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 4.0 + 4.0 ma *5 total maximum clamp current |i clamp | ? 40 ma *5 ?l? level maximum output current i ol ? 15 ma *4 ?l? level average output current i olav ? 4ma*4 ?l? level maximum overall output current i ol ? 100 ma *4 ?l? level average overall output current i olav ? 50 ma *4 ?h? level maximum output current i oh ?? 15 ma *4 ?h? level average output current i ohav ?? 4ma*4 ?h? level maximum overall output current i oh ?? 100 ma *4 ?h? level average overall output current i ohav ?? 50 ma *4 power consumption p d ? 340 mw operating temperature t a ? 40 + 105 c storage temperature t stg ? 55 + 150 c mb90860e series 41 (continued) *5 : ? applicable to pins: p00 to p07, p10 to p1 7, p20 to p27, p30 to p37, p40 to p47, p50 to p57 (evaluation device : p50 to p55) , p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa1 ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instant aneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power s upply is off (not fixed at 0 v) , the power supply is provided from the pins, so t hat incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage ma y not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? sample recommended circuits: warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode mb90860e series 42 2. recommended conditions (v ss = av ss = 0 v) warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smooth capacitor c s 0.1 ? 1.0 f use a ceramic capacitor or capac- itor of better ac characteristics. capacitor at the v cc should be greater than this capacitor. operating temperature t a ? 40 ?+ 105 c c c s c pin connection diagram mb90860e series 43 3. dc characteristics (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) (continued) parameter sym- bol pin condition value unit remarks min typ max input h voltage (at v cc = 5 v 10 % ) v ihs ?? 0.8 v cc ? v cc + 0.3 v port inputs if cmos hysteresis input levels are selected (except p12, p44, p45, p46, p47, p50, p82, p83) v iha ?? 0.8 v cc ? v cc + 0.3 v port inputs if automotive input levels are selected v iht ?? 2.0 ? v cc + 0.3 v port inputs if ttl input levels are selected v ihs ?? 0.7 v cc ? v cc + 0.3 v p12, p50, p82, p85 inputs if cmos input levels are selected v ihi ?? 0.7 v cc ? v cc + 0.3 v p44, p45, p46, p47 in- puts if cmos hysteresis input levels are selected v ihr ?? 0.8 v cc ? v cc + 0.3 v rst input pin (cmos hysteresis) v ihm ?? v cc ? 0.3 ? v cc + 0.3 v md input pin input l voltage (at v cc = 5 v 10 % ) v ils ?? v ss ? 0.3 ? 0.2 v cc v port inputs if cmos hysteresis input levels are selected (except p12, p44, p45, p46, p47, p50, p82, p83) v ila ?? v ss ? 0.3 ? 0.5 v cc v port inputs if automotive input levels are selected v ilt ?? v ss ? 0.3 ? 0.8 v port inputs if ttl input levels are selected v ils ?? v ss ? 0.3 ? 0.3 v cc v p12, p50, p82, p85 inputs if cmos input levels are selected v ili ?? v ss ? 0.3 ? 0.3 v cc v p44, p45, p46, p47 in- puts if cmos hysteresis input levels are selected v ilr ?? v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ?? v ss ? 0.3 ? v ss + 0.3 v md input pin output h voltage v oh normal outputs v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v output h voltage v ohi i 2 c current outputs v cc = 4.5 v, i oh = ? 3.0 ma v cc ? 0.5 ?? v output l voltage v ol normal outputs v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v output l voltage v oli i 2 c current outputs v cc = 4.5 v, i ol = 3.0 ma ?? 0.4 v mb90860e series 44 (continued) (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : the power supply current is m easured with an external clock. parameter sym- bol pin condition value unit remarks min typ max input leak current i il ? v cc = 5.5 v, v ss < v i < v cc ? 1 ? + 1 a pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? except flash devices power supply current* i cc v cc v cc = 5.0 v, internal frequency : 24 mhz, at normal operation. ? 55 70 ma v cc = 5.0 v, internal frequency : 24 mhz, at writing flash memory. ? 70 85 ma flash devices v cc = 5.0 v, internal frequency : 24 mhz, at erasing flash memory. ? 75 90 ma flash devices i ccs v cc = 5.0 v, internal frequency : 24 mhz, at sleep mode. ? 25 35 ma i cts v cc = 5.0 v, internal frequency : 2 mhz, at main timer mode ? 0.3 0.8 ma i ctspll6 v cc = 5.0 v, internal frequency : 24 mhz, at pll timer mode, external frequency = 4 mhz ? 47ma i ccl v cc = 5.0 v internal frequency : 8 khz, at sub operation t a = + 25 c ? 70 140 a i ccls v cc = 5.0 v internal frequency : 8 khz, at sub sleep t a = + 25 c ? 20 50 a i cct v cc = 5.0 v internal frequency : 8 khz, at watch mode t a = + 25 c ? 10 35 a i cch v cc = 5.0 v, at stop mode, t a = + 25 c ? 725 a input capacity c in other than c, av cc , av ss , avrh, avrl, v cc , v ss , ?? 515pf mb90860e series 45 4. ac characteristics (1) clock timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : when selecting the pll clock, the range of clock frequency is limited. use this product within range as mentioned in ?relation among external cl ock frequency and machine clock frequency?. parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using an oscillation circuit x0, x1 3 ? 24 mhz when using an external clock* f cl x0a, x1a ? 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0, x1 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p whl , p wll x0a 5 15.2 ? s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz when using main clock f cpl ?? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns when using main clock t cpl ? 20 122.1 ? s when using sub clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll clock timing mb90860e series 46 ? guaranteed pll operation range guaranteed operation range of mb90860e series * : when using crystal oscillator or ceramic oscillato r, the maximum oscillation clock frequency is 16 mhz 24 5.5 3.5 1.5 4 power supply voltage v cc (v) guaranteed operation range guaranteed pll operation range 4.0 guaranteed a/d converter operation range machine clock f cp (mhz) 24 4.0 16 12 3 4 12 24 internal clock f cp (mhz) external clock f c (mhz) * 4 3 2 1 1/2 (pll off) 8 8 guaranteed oscillation frequency range 1.5 16 6 mb90860e series 47 (2) reset standby input (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0.0 v) * : oscillation time of oscillator is the time that the amplitude reaches 90 % . in the crystal oscillator, the oscillati on time is between several ms and to tens of ms. in ceramic oscillators, the oscillation time is between hundreds of s to several ms. with an external clock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* + 100 s ? ns in stop mode, sub clock mode, sub sleep mode and watch mode 100 ? s in time timer mode t r s tl 0.2 v cc 0.2 v cc 100 s r s t x0 90% of a mplit u de in s tr u ction exec u tion o s cill a tion s t ab iliz a tion w a iting time o s cill a tion time of o s cill a tor intern a l oper a tion clock intern a l re s et 0.2 v cc rst t rstl 0.2 v cc under normal operation: in stop mode, sub clock mode, sub sleep mode, watch mode, power-on: mb90860e series 48 (3) power on reset (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0.0 v) (4) clock output timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation parameter symbol pin condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns f cp = 16 mhz 41.76 ? ns f cp = 24 mhz clk clk t chcl clk ? 20 ? ns f cp = 16 mhz 13 ? ns f cp = 24 mhz v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v hold s ram d a t a if yo u ch a nge the power su pply volt a ge too r a pidly, a power on re s et m a y occ u r. we recommend th a t yo u s t a rt u p s moothly b y re s tr a ining volt a ge s when ch a nging the power su pply volt a ge d u ring oper a tion, as s hown in the fig u re b elow. perform while not us ing the pll clock. however, if volt a ge drop s a re within 1 v/ s , yo u c a n oper a te we recommend a ri s e of 50 mv/m s m a xim u m. clk 2.4 v t cyc 2.4 v 0.8 v t chcl mb90860e series 49 (5) bus timing (read) (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter sym- bol pin condition value unit min max ale pulse width t lhll ale ? t cp /2 ? 10 ? ns valid address ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 ? 20 ? ns ale address valid time t llax ale, ad15 to ad00 t cp /2 ? 15 ? ns valid address rd time t avrl a23 to a16, ad15 to ad00, rd t cp ? 15 ? ns valid address valid data input t avdv a23 to a16, ad15 to ad00 ? 5 t cp /2 ? 60 ns rd pulse width t rlrh rd 3 t cp /2 ? 20 ? ns rd valid data input t rldv rd , ad15 to ad00 ? 3 t cp /2 ? 50 ns rd data hold time t rhdx rd , ad15 to ad00 0 ? ns rd ale time t rhlh rd , ale t cp /2 ? 15 ? ns rd address valid time t rhax rd , a23 to a16 t cp /2 ? 10 ? ns valid address clk time t avch a23 to a16, ad15 to ad00, clk t cp /2 ? 16 ? ns rd clk time t rlch rd , clk t cp /2 ? 15 ? ns ale rd time t llrl ale, rd t cp /2 ? 15 ? ns a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address v il v ih v ih v il read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl mb90860e series 50 (6) bus timing (write) (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit min max valid address wr time t avwl a23 to a16, ad15 to ad00, wr ? t cp ? 15 ? ns wr pulse width t wlwh wr 3 t cp /2 ? 20 ? ns valid data output wr time t dvwh ad15 to ad00, wr 3 t cp /2 ? 20 ? ns wr data hold time t whdx ad15 to ad00, wr 15 ? ns wr address valid time t whax a23 to a16, wr t cp /2 ? 10 ? ns wr ale time t whlh wr , ale t cp /2 ? 15 ? ns wr clk time t wlch wr , clk t cp /2 ? 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl, wrh) t wlwh 0.8 v 2.4 v t avwl a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx mb90860e series 51 (7) ready input timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : if the rdy setup time is insu fficient, use the auto-ready function. parameter sym- bol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns f cp = 16 mhz 32 ? ns f cp = 24 mhz rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd/wr rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il mb90860e series 52 (8) hold timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) note : there is more than 1 cycle fr om when hrq reads in until the hak is changed. parameter symbol pin condition value units min max pin floating hak time t xhal hak ? 30 t cp ns hak time pin valid time t hahv hak t cp 2 t cp ns hak each pin high-z t hahv t xhal 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v mb90860e series 53 (9) uart0/1/2/3/4 (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , v ss = 0.0 v, f cp 24 mhz) notes : ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. parameter symbol pin condition value unit min max serial clock cycle time t scyc sck0 to sck4 internal clock operation output pins are c l = 80 pf + 1 ttl. 8 t cp ? ns sck sot delay time t slov sck0 to sck4, sot0 to sot4 ? 80 + 80 ns valid sin sck t ivsh sck0 to sck4, sin0 to sin4 100 ? ns sck valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck4 external clock operation output pins are c l = 80 pf + 1 ttl. 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck4 4 t cp ? ns sck sot delay time t slov sck0 to sck4, sot0 to sot4 ? 150 ns valid sin sck t ivsh sck0 to sck4, sin0 to sin4 60 ? ns sck valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ? ns internal shift clock mode sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin v il v ih t ivsh v il v ih t shix mb90860e series 54 (10) trigger input timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) parameter symbol pin condition value unit min max input pulse width t trgh t trgl int0 to int15, int0r to int15r, adtg ? 5 t cp ? ns external shift clock mode sck v ih t slsh v il sot 0.8 v 2.4 v t slov sin v il v ih t ivsh v il v ih t shix v ih v il t shsl v il v ih t trgh v il v ih t trgl int0 to int15, int0r to int15r, adtg mb90860e series 55 (11) timer related resource input timing (t a = ? 40 c to + 105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0 v) (12) timer related resource output timing (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , f cp 24 mhz, v ss = 0.0 v) parameter symbol pin condition value unit min max input pulse width t tiwh tin0 to tin3, in0 to in7 ? 4 t cp ? ns t tiwl parameter symbol pin condition value unit min max clk t out change time t to tot0 to tot3, ppg0 to ppgf ? 30 ? ns v il v ih t tiwh v il v ih t tiwl tin0 to tin3, in0 to in7 clk 2.4 v 0.8 v 2.4 v t to tot0 to tot3, ppg0 to ppgf mb90860e series 56 (13) i 2 c timing (t a = ?40 c to +105 c, v cc = 5.0 v 10 % , v ss = 0.0 v) *1 : for use at over 100 khz, set the machine clock to at least 6 mhz. *2 : r,c : pull-up resistor and lo ad capacitor of the scl and sda lines. *3 : the maximum t hddat have only to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *4 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. parameter symbol condition standard-mode fast-mode* 1 unit min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 2 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ?l? width of the scl clock t low 4.7 ? 1.3 ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 3 00.9* 4 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s s da s cl t low t s udat t hd s ta t bu s t hd s ta t hddat t high t s u s ta t s u s to mb90860e series 57 5. a/d converter (t a = ? 40 c to + 105 c, 3.0 v avrh ? avrl, v cc = av cc = 5.0 v 10 % , f cp 24 mhz, v ss = av ss = 0 v) * : if a/d convertor is not operating, a current when cpu is stopped is applicable (v cc = av cc = avrh = 5.0 v) . note : the accuracy gets worse as avrh ? avrl becomes smaller. parameter symbol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero reading voltage v ot an0 to an23 avrl ? 1.5 avrl + 0.5 avrl + 2.5 lsb full scale reading voltage v fst an0 to an23 avrh ? 3.5 avrh ? 1.5 avrh + 0.5 lsb compare time ?? 1.0 ? 16500 s 4.5 v av cc 5.5 v 2.0 4.0 v av cc < 4.5 v sampling time ?? 0.5 ? s 4.5 v av cc 5.5 v 1.2 4.0 v av cc < 4.5 v analog port input current i ain an0 to an23 ? 0.3 ? +0.3 a analog input voltage range v ain an0 to an23 avrl ? avrh v reference voltage range ? avrh avrl + 2.7 ? av cc v ? avrl 0 ? avrh ? 2.7 v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 a* reference voltage current i r avrh ? 600 900 a i rh avrh ?? 5 a* offset between input channels ? an0 to an23 ?? 4lsb mb90860e series 58 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across ze ro-transition line ( ?00 0000 0000? ?00 0000 0001? ) and full-scale transition line ( ?11 1111 1110? ?11 1111 1111? ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required fo r changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an ideal value. a to tal error includes zero transition error, full-scale transition error, and linear error. zero reading voltage : input voltage which results in the minimum conversion value. full scale reading voltage : input voltage which results in the maximum conversion value. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output ?n? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (ideal value) = avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. mb90860e series 59 (continued) 3 ff h 3 fe h 3 fd h 004 h 00 3 h 002 h 001 h avrl avrh avrl avrh n + 1 h n h n ? 1 h n ? 2 h v ot ( a ct ua l me asu rement v a l u e ) { 1 l s b (n ? 1) + v ot } act ua l conver s ion ch a r a cteri s tic s v f s t ( a ct ua l me asu rement v a l u e) v nt ( a ct ua l me asu rement v a l u e) act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s act ua l conver s ion ch a r a cteri s tic s ide a l ch a r a cteri s tic s digit a l o u tp u t digit a l o u tp u t an a log inp u t an a log inp u t v nt ( a ct ua l me asu rement v a l u e) v (n + 1) t ( a ct ua l me asu rement v a l u e) non linearity error differential linearity error non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .? mb90860e series 60 7. notes on a/d converter section use the device with external circuits of the following output impedance for analog inputs : recommended output impedance of external circuits are : approx. 1.5 k ? or lower (4.0 v av cc 5.5 v, sampling period 0.5 s) if an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. if output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. 8. flash memory program/erase characteristics * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16-bit width) programming time ? 16 3600 s except for the over head time of the system programs/erase cycle ? 10000 ?? cycle flash data retention time average t a = + 85 c 20 ?? year * c comparator analog input r 4.5 v av cc 5.5 v : r : = 2.52 k ? , c : = 10.7 pf 4.0 v av cc < 4.5 v : r : = 13.6 k ? , c : = 10.7 pf analog input circuit model note : use the values in the figure only as a guideline. mb90860e series 61 example characteristics mb90f867e, mb90f867es i cc ? v cc i ccl ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i ccs ? v cc i ccls ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i cts ? v cc i cct ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i ctspll6 ? v cc i cch ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at stop i cc (ma) 70 30 10 20 v cc (v) 0 40 50 60 2.5 3.5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 30 10 20 v cc (v) 0 40 50 60 2.5 3.5 4.5 5.5 6.5 f = 8 khz 90 70 80 i ccs (ma) 35 15 5 10 v cc (v) 0 20 25 30 2.5 3.5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccls ( a) 50 15 5 10 v cc (v) 0 20 30 40 2.5 3.5 4.5 5.5 6.5 f = 8 khz 45 25 35 i cts ( a) 400 150 50 100 v cc (v) 0 200 300 2.5 3.5 4.5 5.5 6.5 f = 2 mhz 350 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3.5 4.5 5.5 6.5 f = 8 khz 18 14 4 2 i ctspll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3.5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3.5 4.5 5.5 6.5 9 7 3 4 mb90860e series 62 mb90867e, mb90867es i cc ? v cc i ccl ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i ccs ? v cc i ccls ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i cts ? v cc i cct ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at external clock operating f = internal operation frequency i ctspll6 ? v cc i cch ? v cc t a = + 25 c, at external clock operating f = internal operation frequency t a = + 25 c, at stop i cc (ma) 70 30 10 20 v cc (v) 0 40 50 60 2.5 3.5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl ( a) 100 30 10 20 v cc (v) 0 40 50 60 2.5 3.5 4.5 5.5 6.5 f = 8 khz 90 70 80 i ccs (ma) 35 15 5 10 v cc (v) 0 20 25 30 2.5 3.5 4.5 5.5 6.5 f = 24 mhz f = 20 mhz f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccls ( a) 50 15 5 10 v cc ( v ) 0 20 30 40 2.5 3.5 4.5 5.5 6.5 f = 8 khz 45 25 35 i cts ( a) 400 150 50 100 v cc (v) 0 200 300 2.5 3.5 4.5 5.5 6.5 f = 2 mhz 350 250 i cct ( a) 20 10 6 8 v cc (v) 0 12 16 2.5 3.5 4.5 5.5 6.5 f = 8 khz 18 14 4 2 i ctspll6 (ma) 10 3 1 2 v cc (v) 0 4 8 2.5 3.5 4.5 5.5 6.5 f = 24 mhz 9 6 5 7 i cch ( a) 10 5 1 2 v cc (v) 0 6 8 2.5 3.5 4.5 5.5 6.5 9 7 3 4 mb90860e series 63 i/o characteristics (v cc ? v oh ) ? i oh v ol ? i ol t a = + 25 c, v cc = 4.5 v t a = + 25 c, v cc = 4.5 v automotive v in ? v cc cmos v in ? v cc t a = + 25 c uart-sin pin, other than i 2 c pin t a = + 25 c ttl v in ? v cc cmos v in ? v cc t a = + 25 c uart-sin pin, i 2 c pin t a = + 25 c v cc v oh (mv) 800 300 100 200 i oh (ma) 0 400 500 600 024 7 10 700 13 6 589 v ol (mv) 1000 300 100 200 i ol (ma) 0 400 500 600 900 700 800 024 7 10 13 6 589 v in (v) 5.0 1.5 0.5 1.0 v cc (v) 0.0 2.0 3.0 3.5 2.5 2.5 3.5 4.5 5.5 6.5 3.0 4.0 5.0 6.0 7.0 4.0 4.5 v iha v ila v in (v) 5.0 2.5 1.5 2.0 v cc (v) 0.0 3.0 4.0 2.5 3.5 4.5 5.5 6.5 4.5 3.5 1.0 0.5 v ihs v ils 3.0 4.0 5.0 6.0 7.0 v in (v) 2.5 0.8 0.3 0.5 v cc (v) 0.0 1.0 2.0 2.5 3.5 4.5 5.5 6.5 2.3 1.5 1.3 1.8 3.0 4.0 5.0 6.0 7.0 v iht v ilt v in (v) 5.0 2.5 0.5 1.0 v cc (v) 0.0 3.0 4.0 4.5 3.5 1.5 2.0 2.5 3.5 4.5 5.5 6.5 3.0 4.0 5.0 6.0 7.0 v ihs v ils mb90860e series 64 ordering information part number package remarks mb90f867epf 100-pin plastic qfp (fpt-100p-m06) flash memory product mb90f867espf mb90f867epfv 100-pin plastic lqfp (fpt-100p-m05) mb90f867espfv mb90867epf 100-pin plastic qfp (fpt-100p-m06) mask rom product MB90867ESPF mb90867epfv 100-pin plastic lqfp (fpt-100p-m05) MB90867ESPFv mb90v340e-101 299-pin ceramic pga (pga-299c-a01) evaluation product mb90v340e-102 mb90860e series 65 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. mb90860e series 66 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.65g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m05) (fpt-100p-m05) c 200 3 fujit s u limited f100007 s -c-4-6 14.000.10(.551.004) s q 16.000.20(.6 3 0.00 8 ) s q 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.1450.055 (.0057.0022) 0.0 8 (.00 3 ) "a" index .059 ?.004 +.00 8 ?0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. mb90860e series f0610 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept. |
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